The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Oct. 31, 2013
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Im-Cheol Ha, Hsinchu, TW;

Jen-Fu Su, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/10 (2006.01); G11C 8/00 (2006.01); G11C 7/12 (2006.01); G11C 5/06 (2006.01); G11C 11/4094 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 13/00 (2006.01); G11C 16/24 (2006.01); G11C 11/408 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 13/0026 (2013.01); G11C 16/24 (2013.01); G11C 13/0023 (2013.01); G11C 11/4087 (2013.01); G11C 7/12 (2013.01); G11C 16/08 (2013.01); G11C 8/10 (2013.01);
Abstract

A memory device includes a memory cell array and a column decoder. The memory cell array includes a plurality of even local bit lines and a plurality of odd local bit lines. The column decoder includes a plurality of even pass transistors, a plurality of even clamp transistors, a plurality of odd pass transistors, and a plurality of odd clamp transistors. Each of the even clamp transistors has a control terminal coupled to an even clamp line, a first terminal coupled to a respective one of the even local bit lines, and a second terminal coupled to a ground voltage. Each of the odd clamp transistors has a control terminal coupled to an odd clamp line, a first terminal coupled to a respective one of the odd local bit lines, and a second terminal coupled to the ground voltage.


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