The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Jul. 01, 2013
Applicant:

Sts Semiconductor & Telecommunications Co., Ltd., Cheonan-si, Chungcheongnam-do, KR;

Inventors:

Daesik Choi, Seoul, KR;

Seung Hoon Oh, Cheonan-si, KR;

Assignee:

STS Semiconductor & Telecommunications Co., Ltd., Cheonan-si, Chungcheongnam-do, KR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/22 (2006.01); H01L 23/10 (2006.01); H01L 21/44 (2006.01); H01L 21/50 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 25/50 (2013.01);
Abstract

A stacked integrated circuit package and a method for manufacturing the same are provided. The stacked integrated circuit package includes a first integrated circuit package comprising a first substrate, a first semiconductor chip, and a first molding portion, an interposer mounted on the first substrate to be electrically connected to the circuit pattern of the first substrate by a first solder bump, the interposer being provided with an opening to accommodate the first semiconductor chip, and a second integrated circuit package stacked on the first integrated circuit package and the interposer and electrically connected to the interposer by a second solder bump, the second integrated circuit package comprising a second substrate, a second semiconductor chip, and a second molding portion.


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