The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Mar. 08, 2012
Applicants:

Wei-ren Chen, Pingtung County, TW;

Te-hsun Hsu, Hsinchu County, TW;

Shih-chen Wang, Taipei, TW;

Hsin-ming Chen, Hsinchu, TW;

Ching-sung Yang, Hsinchu, TW;

Inventors:

Wei-Ren Chen, Pingtung County, TW;

Te-Hsun Hsu, Hsinchu County, TW;

Shih-Chen Wang, Taipei, TW;

Hsin-Ming Chen, Hsinchu, TW;

Ching-Sung Yang, Hsinchu, TW;

Assignee:

Ememory Technology Inc., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract

An erasable programmable single-poly nonvolatile memory includes a first PMOS transistor comprising a select gate, a first p-type doped region, and a second p-type doped region, wherein the select gate is connected to a select gate voltage, and the first p-type doped region is connected to a source line voltage; a second PMOS transistor comprising the second p-type doped region, a third p-type doped region, and a floating gate, wherein the third p-type doped region is connected to a bit line voltage; and an erase gate region adjacent to the floating gate, wherein the erase gate region is connected to an erase line voltage.


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