The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2015
Filed:
Jul. 08, 2012
Yung-fa Lin, Hsinchu, TW;
Shou-yi Hsu, Hsinchu County, TW;
Meng-wei Wu, Hsinchu, TW;
Main-gwo Chen, Hsinchu County, TW;
Chia-hao Chang, Hsinchu, TW;
Chia-wei Chen, Taipei, TW;
Yung-Fa Lin, Hsinchu, TW;
Shou-Yi Hsu, Hsinchu County, TW;
Meng-Wei Wu, Hsinchu, TW;
Main-Gwo Chen, Hsinchu County, TW;
Chia-Hao Chang, Hsinchu, TW;
Chia-Wei Chen, Taipei, TW;
Anpec Electronics Corporation, Hsinchu Science Park, Hsin-Chu, TW;
Abstract
The present invention provides a trench type power transistor device including a substrate, an epitaxial layer, a doped diffusion region, a doped source region, and a gate structure. The substrate, the doped diffusion region, and the doped source region have a first conductivity type, and the substrate has an active region and a termination region. The epitaxial layer is disposed on the substrate, and has a second conductivity type. The epitaxial layer has a through hole disposed in the active region. The doped diffusion region is disposed in the epitaxial layer at a side of the through hole, and is in contact with the substrate. The doped source region is disposed in the epitaxial layer disposed right on the doped diffusion region, and the gate structure is disposed in the through hole between the doped diffusion region and the doped source region.