The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Aug. 04, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Robert J. Gauthier, Jr., Hinesburg, VT (US);

Tom C. Lee, Essex Junction, VT (US);

Junjun Li, Williston, VT (US);

Souvick Mitra, Essex Junction, VT (US);

Christopher Stephen Putnam, Hinesburg, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/332 (2006.01); H01L 21/76 (2006.01); H01L 21/8249 (2006.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/8249 (2013.01); H01L 27/0255 (2013.01); H01L 27/0251 (2013.01); H01L 27/0266 (2013.01); H01L 29/6609 (2013.01); H01L 29/66371 (2013.01); H01L 29/66795 (2013.01); H01L 21/823431 (2013.01);
Abstract

Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.


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