The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

May. 08, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Tongsuk Kim, Hwaseong-si, KR;

Jangwoo Lee, Cheonan-si, KR;

Heeseok Lee, Yongin-si, KR;

Kyoungsei Choi, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 23/06 (2006.01); H01L 23/10 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/34 (2006.01); H01L 25/065 (2006.01); H01L 23/36 (2006.01); H01L 23/42 (2006.01);
U.S. Cl.
CPC ...
H01L 23/06 (2013.01); H01L 23/10 (2013.01); H01L 23/3128 (2013.01); H01L 23/552 (2013.01); H01L 23/49816 (2013.01); H01L 21/563 (2013.01); H01L 23/34 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/16172 (2013.01); H01L 2924/16251 (2013.01); H01L 2225/06568 (2013.01); H01L 23/36 (2013.01); H01L 23/42 (2013.01); A01L 23/562 (2013.01);
Abstract

A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided.


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