The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2015
Filed:
May. 11, 2012
Choongyeun Cho, Beacon, NY (US);
Daeik Kim, Fishkill, NY (US);
Jonghae Kim, Fishkill, NY (US);
Moon J. Kim, Wappingers Falls, NY (US);
Jean-olivier Plouchart, New York, NY (US);
Robert E. Trzcinski, Rhinebeck, NY (US);
Choongyeun Cho, Beacon, NY (US);
Daeik Kim, Fishkill, NY (US);
Jonghae Kim, Fishkill, NY (US);
Moon J. Kim, Wappingers Falls, NY (US);
Jean-Olivier Plouchart, New York, NY (US);
Robert E. Trzcinski, Rhinebeck, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.