The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2015

Filed:

Mar. 02, 2012
Applicants:

Yusuke Maeyama, Iruma, JP;

Ryohei Osawa, Tokorozawa, JP;

Yoshitaka Araki, Nishimurayama-gun, JP;

Yoshiyuki Watanabe, Iruma, JP;

Inventors:

Yusuke Maeyama, Iruma, JP;

Ryohei Osawa, Tokorozawa, JP;

Yoshitaka Araki, Nishimurayama-gun, JP;

Yoshiyuki Watanabe, Iruma, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/872 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/872 (2013.01); H01L 29/0619 (2013.01); H01L 29/1608 (2013.01);
Abstract

A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.


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