The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

Dec. 22, 2010
Applicant:

Jerry Pirog, Easton, PA (US);

Inventor:

Jerry Pirog, Easton, PA (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 9/38 (2006.01); G06F 9/46 (2006.01); G06F 12/08 (2006.01); G06F 15/167 (2006.01); H04L 12/54 (2013.01); H04L 12/853 (2013.01); H04L 12/851 (2013.01);
U.S. Cl.
CPC ...
G06F 9/3885 (2013.01); G06F 9/3851 (2013.01); G06F 9/46 (2013.01); G06F 12/0842 (2013.01); G06F 12/0844 (2013.01); G06F 15/167 (2013.01); H04L 12/56 (2013.01); H04L 47/2416 (2013.01); H04L 47/2441 (2013.01); G06F 12/0815 (2013.01);
Abstract

Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units.


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