The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

Mar. 23, 2010
Applicants:

Philipp Steinmann, Richardson, TX (US);

Manfred Schiekofer, Freising, DE;

Michael Kraus, Marzling, DE;

Thomas Scharnagl, Tiefenbach, DE;

Wolfgang Schwartz, Au in der Hallertau, DE;

Inventors:

Philipp Steinmann, Richardson, TX (US);

Manfred Schiekofer, Freising, DE;

Michael Kraus, Marzling, DE;

Thomas Scharnagl, Tiefenbach, DE;

Wolfgang Schwartz, Au in der Hallertau, DE;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/74 (2006.01); H01L 21/02 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 21/743 (2013.01); H01L 21/02532 (2013.01); H01L 21/02639 (2013.01); H01L 21/84 (2013.01);
Abstract

Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.


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