The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Sep. 29, 2012
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Fangxing Wei, Portland, OR (US);
Subratakumar Mandal, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 25/00 (2006.01); H04L 25/40 (2006.01); H04B 1/16 (2006.01);
U.S. Cl.
CPC ...
H04B 1/16 (2013.01);
Abstract
Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.