The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Oct. 15, 2013
Applicant:

Integrated Silicon Solution, Inc., Milpitas, CA (US);

Inventors:

MingShiang Wang, Cupertino, CA (US);

Kyoung Chon Jin, San Ramon, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/30 (2006.01); G11C 7/14 (2006.01); G11C 16/34 (2006.01); G11C 29/00 (2006.01); G11C 29/08 (2006.01); G11C 5/14 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G11C 7/14 (2013.01); G11C 29/028 (2013.01); G11C 29/50004 (2013.01);
Abstract

A method to trim a reference voltage source formed on an integrated circuit includes configuring the integrated circuit in a test mode; providing a power supply voltage and a trim code sequence to the integrated circuit where the power supply voltage is provided by a precision reference voltage source; generating a target voltage on the integrated circuit using the power supply voltage; generate a reference voltage using the reference voltage source formed on the integrated circuit; applying one or more trim codes in the trim code sequence to the reference voltage source to adjust the reference voltage; comparing the reference voltage generated based on the trim codes to the target voltage; asserting a latch signal in response to a determination that the reference voltage generated based on a first trim code is equal to the target voltage; and storing the first trim code in response to the latch signal being asserted.


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