The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
May. 04, 2007
Philippe Renaud, Cugneaux, FR;
Patrice Besse, Toulouse, FR;
Amaury Gendron, Toulouse, FR;
Nicolas Nolhier, Espanes, FR;
Philippe Renaud, Cugneaux, FR;
Patrice Besse, Toulouse, FR;
Amaury Gendron, Toulouse, FR;
Nicolas Nolhier, Espanes, FR;
Freescale Semiconductor, Inc., Austin, TX (US);
Le Centre National de la Recherché Scientifique (CNRS), Paris, FR;
Abstract
An ESD protection device, which is arranged to be active at a triggering voltage (Vt) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth. The floating region is separated from the well region by a predetermined distance, a value of which is selected such that the floating region is located within a depletion region of a PN junction between the well region and the semiconductor layer when the ESD protection device is active. The floating region has a doping concentration selected such that the floating region is not fully depleted when the ESD protection device is active and the predetermined depth is selected such that the floating region modifies a space charge region near the PN junction. An ESD protection device according to a second embodiment is also disclosed.