The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Mar. 16, 2013
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Nobuyuki Shirai, Takasaki, JP;

Nobuyoshi Matsuura, Takasaki, JP;

Yoshito Nakazawa, Isesaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/872 (2006.01); H01L 29/45 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/08 (2006.01); H01L 29/47 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8725 (2013.01); H01L 29/456 (2013.01); H01L 29/7811 (2013.01); H01L 29/1095 (2013.01); H01L 29/782 (2013.01); H01L 29/872 (2013.01); H01L 29/7802 (2013.01); H01L 29/0615 (2013.01); H01L 29/402 (2013.01); H01L 29/7806 (2013.01); H01L 29/7823 (2013.01); H01L 29/407 (2013.01); H01L 29/7813 (2013.01); H01L 29/0847 (2013.01); H01L 29/0619 (2013.01); H01L 29/47 (2013.01); H01L 29/0696 (2013.01); H01L 29/0878 (2013.01);
Abstract

A semiconductor device has a semiconductor substrate with a plurality of transistor cell regions. Each transistor cell region includes a plurality of trenches disposed in the semiconductor substrate, a well region between the plurality of trenches, and a source region of a MOSFET in the well region. A source electrode of the MOSFET is in contact with a top surface of the source region in each of the plurality of transistor cell regions. The source electrode is in contact with a part of a main surface of the semiconductor substrate so as to form a Schottky junction in a Schottky cell region disposed between the plurality of transistor cell regions. The Schottky junction is lower than a portion of the main surface between the Schottky junction and one of the transistor cell regions.


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