The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Aug. 26, 2013
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Guy Cohen, Mohegan Lake, NY (US);

Michael A. Guillorn, Yorktown Heights, NY (US);

Alfred Grill, White Plains, NY (US);

Leathen Shi, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/775 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01); H01L 29/423 (2006.01); B82Y 40/00 (2011.01);
U.S. Cl.
CPC ...
H01L 29/775 (2013.01); B82Y 40/00 (2013.01); H01L 29/66484 (2013.01); H01L 29/0673 (2013.01); H01L 29/78696 (2013.01); Y10S 977/938 (2013.01); H01L 29/785 (2013.01); Y10S 977/888 (2013.01); H01L 29/42392 (2013.01); Y10S 977/762 (2013.01);
Abstract

A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.


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