The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Nov. 28, 2011
Applicants:

Doo-young Lee, Seoul, KR;

Ki IL Kim, Yongin-si, KR;

Myeong-cheol Kim, Suwon-si, KR;

Do-hyoung Kim, Hwaseong-si, KR;

Do-hsing Lee, Hwaseong-si, KR;

Inventors:

Doo-Young Lee, Seoul, KR;

Ki Il Kim, Yongin-si, KR;

Myeong-Cheol Kim, Suwon-si, KR;

Do-Hyoung Kim, Hwaseong-si, KR;

Do-Hsing Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/339 (2006.01); H01L 21/768 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 21/76832 (2013.01); H01L 21/76897 (2013.01); H01L 21/76829 (2013.01); H01L 21/76895 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.


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