The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Jul. 06, 2010
Applicant:

Romi O. Mayder, San Jose, CA (US);

Inventor:

Romi O. Mayder, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01K 3/10 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); G01R 31/28 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4617 (2013.01); H05K 1/0206 (2013.01); G01R 31/2863 (2013.01); H05K 1/113 (2013.01); H05K 2201/096 (2013.01); H05K 2203/0733 (2013.01);
Abstract

A method, and apparatus resulting from the method, for fabricating a circuit board suitable for mounting electronic components. The method includes drilling a plurality of through-holes in a plurality of dielectric sheets, forming a conductive film on at least one side of each of the plurality of dielectric sheets, and substantially filling each of the plurality of through holes with a conductive material. The conductive material is both electrically and thermally uninterrupted from a first face to a second face of each of the plurality of dielectric sheets. The plurality of dielectric sheets are then sequentially mounted, one atop another, to form the circuit board. The sequential mounting step is performed after the steps of drilling the plurality of through-holes, forming the conductive layer, and substantially filling the plurality of through-holes.


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