The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

May. 29, 2012
Applicants:

Tryggve Fossum, Northborough, MA (US);

George Chrysos, Milford, MA (US);

Todd A. Dutton, Southborough, MA (US);

Inventors:

Tryggve Fossum, Northborough, MA (US);

George Chrysos, Milford, MA (US);

Todd A. Dutton, Southborough, MA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 9/38 (2006.01); G06F 9/50 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3836 (2013.01); G06F 9/3802 (2013.01); G06F 9/5094 (2013.01); Y02B 60/1282 (2013.01); G06F 9/3869 (2013.01); G06F 9/30181 (2013.01); G06F 1/3287 (2013.01); Y02B 60/1278 (2013.01); G06F 1/3203 (2013.01); G06F 9/5061 (2013.01);
Abstract

A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.


Find Patent Forward Citations

Loading…