The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Dec. 19, 2012
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Min-Soo Kim, Gyeonggi-do, KR;

Young-Jin Lee, Gyeonggi-do, KR;

Sung-Jin Whang, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 29/66 (2006.01); G11C 16/04 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 29/66833 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 29/7926 (2013.01); H01L 27/11582 (2013.01);
Abstract

This technology relates to a nonvolatile memory device and a method for fabricating the same. The nonvolatile memory device may include a pipe connection gate electrode configured to have a lower part buried in a groove formed in a substrate, one or more pipe channel layers formed within the pipe connection gate electrode, pairs of main channel layers each coupled with the pipe channel layer and extended in a direction substantially perpendicular to the substrate; and a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel layers. In accordance with this technology, a lower part of the pipe connection gate electrode is buried in the substrate. Accordingly, electric resistance may be reduced because the pipe connection gate electrode may have an increased volume without a substantial increase of the height.


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