The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2014
Filed:
Jul. 24, 2012
Method for forming gate structure, method for forming semiconductor device, and semiconductor device
Hong Yang, Beijing, CN;
Xueli MA, Beijing, CN;
Wenwu Wang, Beijing, CN;
Kai Han, Beijing, CN;
Xiaolei Wang, Beijing, CN;
Huaxiang Yin, Beijing, CN;
Jiang Yan, Newburg, NY (US);
Hong Yang, Beijing, CN;
Xueli Ma, Beijing, CN;
Wenwu Wang, Beijing, CN;
Kai Han, Beijing, CN;
Xiaolei Wang, Beijing, CN;
Huaxiang Yin, Beijing, CN;
Jiang Yan, Newburg, NY (US);
Abstract
A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.