The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2014
Filed:
Jul. 20, 2012
Ji-hyoung Yoo, Cupertino, CA (US);
Ze-qiang Yao, Santa Clara, CA (US);
Jeesung Jung, San Jose, CA (US);
Haifeng Yang, Shanghai, CN;
Ji-Hyoung Yoo, Cupertino, CA (US);
Ze-Qiang Yao, Santa Clara, CA (US);
Jeesung Jung, San Jose, CA (US);
Haifeng Yang, Shanghai, CN;
Monolithic Power Systems, Inc., San Jose, CA (US);
Abstract
Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures.