The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2014

Filed:

Feb. 15, 2012
Applicants:

Martin Doerr, Schwaigern, DE;

Benedikt Geukes, Stuttgart, DE;

Holger Horbach, Stuttgart, DE;

Matteo Michel, Chemnitz, DE;

Manfred Walz, Boeblingen, DE;

Inventors:

Martin Doerr, Schwaigern, DE;

Benedikt Geukes, Stuttgart, DE;

Holger Horbach, Stuttgart, DE;

Matteo Michel, Chemnitz, DE;

Manfred Walz, Boeblingen, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/318572 (2013.01);
Abstract

A scan circuit (JTAG 1149 extension) for a microprocessor utilizes transport logic and scan chains which operate at a faster clock speed than the external JTAG clock. The transport logic converts the input serial data stream (TDI) into input data packets which are sent to scan chains, and converts output data packets into an output data stream (TDO). The transport logic includes a deserializer having a sliced input buffer, and a serializer having a sliced output buffer. The scan circuit can be used for testing with boundary scan latches, or to control internal functions of the microprocessor. Local clock buffers can be used to distribute the clock signals, controlled by thold signals generated from oversampling of the external clock. The result is a JTAG scanning system which is not limited by the external JTAG clock speed, allowing multiple internal scan operations to complete within a single external JTAG cycle.


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