The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Dec. 29, 2005
Hong Wang, Santa Clara, CA (US);
John Shen, San Jose, CA (US);
Hong Jiang, San Jose, CA (US);
Richard Hankins, San Jose, CA (US);
Per Hammarlund, Hillsboro, OR (US);
Dion Rodgers, Hillsboro, OR (US);
Gautham Chinya, Hillsboro, OR (US);
Baiju Patel, Portland, OR (US);
Shiv Kaushik, Portland, OR (US);
Bryant Bigbee, Scottsdale, AZ (US);
Gad Sheaffer, Haifa, IL;
Yoav Talgam, Tel-Aviv, IL;
Yuval Yosef, Hadera, IL;
James P. Held, Portland, OR (US);
Hong Wang, Santa Clara, CA (US);
John Shen, San Jose, CA (US);
Hong Jiang, San Jose, CA (US);
Richard Hankins, San Jose, CA (US);
Per Hammarlund, Hillsboro, OR (US);
Dion Rodgers, Hillsboro, OR (US);
Gautham Chinya, Hillsboro, OR (US);
Baiju Patel, Portland, OR (US);
Shiv Kaushik, Portland, OR (US);
Bryant Bigbee, Scottsdale, AZ (US);
Gad Sheaffer, Haifa, IL;
Yoav Talgam, Tel-Aviv, IL;
Yuval Yosef, Hadera, IL;
James P. Held, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where the accelerator is a heterogeneous resource with respect to the instruction sequencer. An interface may be used to provide the communication between these resources. Via such a communication mechanism a user-level application may directly communicate with the accelerator without operating system support. Further, the instruction sequencer and the accelerator may perform operations in parallel. Other embodiments are described and claimed.