The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2014
Filed:
Feb. 05, 2014
Applicants:
Tsung-yi Huang, HsinChu, TW;
Chien-hao Huang, Magong, TW;
Inventors:
Tsung-Yi Huang, HsinChu, TW;
Chien-Hao Huang, Magong, TW;
Assignee:
Richtek Technology Corporation, Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 29/66689 (2013.01); H01L 29/7816 (2013.01); H01L 29/0878 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01);
Abstract
The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.