The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2014
Filed:
Mar. 05, 2014
Cadence Design Systems, Inc., San Jose, CA (US);
Pradeep Goyal, Uttar Pradesh, IN;
Alok Jain, New Delhi, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present disclosure relates to a method for debugging in the formal verification of an integrated circuit design. The method may include providing, via a computing device, an electronic design associated with the integrated circuit. Embodiments may further include splitting one or more nets in a cone of influence of a target associated with the electronic design. For each split net, embodiments may include placing a constraint that re-joins the net. Embodiments may also include identifying a local region of the electronic design for which the target is unreachable. During formal verification, embodiments may include ignoring all constraints associated with the local region of the electronic design.