The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Nov. 29, 2011
Applicants:

Jeffrey Herman, Sunnyvale, CA (US);

Krishna Sitaraman, San Jose, CA (US);

Jia an Huang, Toronto, CA;

Stephen D. Presant, San Jose, CA (US);

Ali Ibrahim, Oakland, CA (US);

Ashwini Dwarakanath, San Jose, CA (US);

Inventors:

Jeffrey Herman, Sunnyvale, CA (US);

Krishna Sitaraman, San Jose, CA (US);

Jia An Huang, Toronto, CA;

Stephen D. Presant, San Jose, CA (US);

Ali Ibrahim, Oakland, CA (US);

Ashwini Dwarakanath, San Jose, CA (US);

Assignees:

ATI Technologies ULC, Markham, Ontario, CA;

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
Abstract

Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.


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