The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2014
Filed:
Jul. 13, 2011
Hubertus Antonius Geraets, Arendonk, BE;
Gerardus Carolus Johannus Hofmans, Eindhoven, NL;
Sven Gunnar Krister Magnusson, Warmbad-Villach, AT;
Hubertus Antonius Geraets, Arendonk, BE;
Gerardus Carolus Johannus Hofmans, Eindhoven, NL;
Sven Gunnar Krister Magnusson, Warmbad-Villach, AT;
ASML Netherlands B.V., Veldhoven, NL;
Abstract
A method of calibrating an inspection apparatus. Obtaining a surface level measurements (LS) at respective level sensing locations LS(x,y). Determining focus settings (LP, LP) for exposure field regions (EF, EF) in accordance with surface level measurements (LS, LS) having level sensing locations corresponding to the respective exposure field region. Exposing exposure field regions (EF, EF) with focus offsets (FO, FO) defined with reference to the respective focus settings (LP, LP) to produce target patterns at respective target locations. Obtaining focus-dependent property measurements, such as Critical Dimension (CD) and/or side wall angle (SWA) of the target patterns measured using the inspection apparatus; and calibrating the inspection apparatus using the focus-dependent property measurements (CD/SWA) and the respective focus offsets (FO, FO). The calibration uses surface level measurements (e.g., LS()) having a level sensing location (e.g., LSL()) corresponding to the respective target location (TL). Each offset value is thus corrected in the calibration for the local wafer stack unflatness present during exposure.