The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2014

Filed:

Apr. 28, 2014
Applicant:

Microsemi Semiconductor Ulc, Kanata, CA;

Inventors:

Krste Mitric, Ottawa, CA;

Paul Schram, Bergen op Zoom, NL;

Tanmay Zargar, Austin, TX (US);

David Colby, Austin, TX (US);

Cathy Zhang, Ottawa, CA;

Robertus van der Valk, Capelle AAn de Ijssel, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01); H03L 7/10 (2006.01);
U.S. Cl.
CPC ...
H03L 7/10 (2013.01);
Abstract

A phase-locked loop to is simultaneously synchronized to high and low frequency clocks by (i) locking an output of the phase-locked loop to a high-frequency reference clock, (ii) measuring at a high rate a first phase difference between the high-frequency reference clock and the output of the phase-locked loop, (iii) measuring at a high rate a second phase difference between a low-frequency reference clock and the output of the phase-locked loop; (iv) computing at a low rate from said first and second phase differences a third phase difference between the high-frequency and low frequency clocks; (v) combining at a low rate said third phase difference with said second phase-difference to obtain a total phase difference; and (vi) adjusting the output of the phase-locked loop at a low rate to reduce the obtained total phase difference.


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