The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Aug. 18, 2011
Applicants:

Abhijeet Ashok Chachad, Plano, TX (US);

Raguram Damodaran, Plano, TX (US);

Jonathan (Son) Hung Tran, Murphy, TX (US);

Timothy David Anderson, Dallas, TX (US);

Sanjive Agarwala, Plano, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

Raguram Damodaran, Plano, TX (US);

Jonathan (Son) Hung Tran, Murphy, TX (US);

Timothy David Anderson, Dallas, TX (US);

Sanjive Agarwala, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 7/483 (2006.01); G06F 12/02 (2006.01); G06F 1/32 (2006.01); G06F 9/30 (2006.01); H03M 13/35 (2006.01); H03M 13/29 (2006.01); G06F 11/10 (2006.01); H03K 19/00 (2006.01); H03K 21/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1064 (2013.01); G06F 7/483 (2013.01); G06F 12/0246 (2013.01); G06F 1/3296 (2013.01); G06F 9/3012 (2013.01); H03M 13/353 (2013.01); H03M 13/2903 (2013.01); Y02B 60/32 (2013.01); H03K 19/0016 (2013.01); H03K 21/00 (2013.01);
Abstract

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.


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