The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Mar. 15, 2013
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Tokumasa Hara, Kawasaki, JP;

Hiroshi Sukegawa, Tokyo, JP;

Toshio Fujisawa, Yokohama, JP;

Shirou Fujita, Kamakura, JP;

Masaki Unno, Yokohama, JP;

Masanobu Shirakawa, Chigasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/06 (2013.01); G11C 16/3445 (2013.01); G11C 16/16 (2013.01); G11C 16/344 (2013.01); G11C 16/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes memory cell arrays each including blocks. The block is unit of erase and includes string-groups. Each string-group includes strings each including a first transistor, memory cell transistors, a second transistor coupled in series. The first transistor is connected to different bit line and the second transistor is connected to same source line. The memory cell arrays are provided with different respective block address signals. The memory cell arrays are provided with different respective string address signals. Each of the block address signals specifies one block. Each of the string address signals specifies one string-group.


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