The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Mar. 05, 2013
Applicant:

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Francesco La Rosa, Rousset, FR;

Yoann Goasduff, Fuveau, FR;

Stephan Niel, Greasque, FR;

Arnaud Regnier, Les Taillades, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); G11C 16/04 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7889 (2013.01); G11C 16/0483 (2013.01); H01L 29/66825 (2013.01); G11C 16/0425 (2013.01); H01L 27/11524 (2013.01);
Abstract

The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.


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