The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2014
Filed:
May. 19, 2009
Applicants:
Michael Stoisiek, Erlangen, DE;
Michael Gross, Erlangen, DE;
Inventors:
Michael Stoisiek, Erlangen, DE;
Michael Gross, Erlangen, DE;
Assignee:
X-Fab Semiconductor Foundries AG, Erfurt, DE;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 29/78 (2006.01); H01L 21/67 (2006.01); H01L 29/423 (2006.01); G05D 23/19 (2006.01); H03K 17/14 (2006.01); H03K 17/08 (2006.01);
U.S. Cl.
CPC ...
G05D 23/19 (2013.01); H01L 29/7802 (2013.01); H01L 21/67098 (2013.01); H01L 29/4238 (2013.01); H01L 29/7831 (2013.01); H01L 21/67248 (2013.01); H03K 17/145 (2013.01); H01L 29/7816 (2013.01); H03K 2017/0806 (2013.01);
Abstract
Described is a method for adjusting an operating temperature of MOS power components composed of a plurality of identical individual cells and a component for carrying out the method. As a characteristic feature, the gate electrode network () of the active chip region is subdivided into several gate electrode network sectors (B, B, B) which are electrically isolated from one another by means of isolating points and to each of which a different gate voltage is fed via corresponding contacts.