The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 02, 2014

Filed:

Aug. 31, 2007
Applicants:

Huajie Chen, Danbury, CT (US);

Dureseti Chidambarrao, Weston, CT (US);

Omer H. Dokumaci, Wappingers Falls, NY (US);

Inventors:

Huajie Chen, Danbury, CT (US);

Dureseti Chidambarrao, Weston, CT (US);

Omer H. Dokumaci, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 27/118 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7848 (2013.01); H01L 29/66636 (2013.01); H01L 29/1054 (2013.01); H01L 21/823814 (2013.01); H01L 29/66628 (2013.01); H01L 21/823807 (2013.01);
Abstract

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.


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