The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2014
Filed:
Jan. 10, 2013
Globalfoundries Inc., Grand Cayman, KY;
Ashish K. Jha, Clifton Park, NY (US);
Tae-Hoon Kim, Malta, NY (US);
Tae Hoon Lee, Clifton Park, NY (US);
Chang Ho Maeng, Clifton Park, NY (US);
Songkram Srivathanakul, Waterford, NY (US);
Haiting Wang, Clifton Park, NY (US);
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Abstract
In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.