The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Apr. 13, 2009
Applicants:

Taranjit Singh Kukal, Delhi, IN;

Nikhil Gupta, New Delhi, IN;

Steve Durrill, Campbell, CA (US);

Vikrant Khanna, Noida, IN;

Dingru Xiao, Shanghai, CN;

Inventors:

Taranjit Singh Kukal, Delhi, IN;

Nikhil Gupta, New Delhi, IN;

Steve Durrill, Campbell, CA (US);

Vikrant Khanna, Noida, IN;

Dingru Xiao, Shanghai, CN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A design system provides data structures to store parameters of physical structures that can be viewed and modified through a graphical design interface. Certain of the structures of the physical system may be partitioned into a subsystem such that the data describing the subsystem includes physical topology data defining relative locations of the structures in the physical system. The physical topology data is back-annotated into a logical topology, such as in accordance with a predefined logical topology template. The logical data abstraction of the circuit design is kept synchronized with the physical data and presented in a logical topology that is kept legible through the prudent selection of logical topologies representing the physical subsystem design.


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