The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2014
Filed:
Nov. 07, 2008
Chung-lun Liu, Taichung Hsien, TW;
Jung-pin Huang, Taichung Hsien, TW;
Yi-feng Chang, Taichung, TW;
Chin-huang Chang, Taichung Hsien, TW;
Chung-Lun Liu, Taichung Hsien, TW;
Jung-Pin Huang, Taichung Hsien, TW;
Yi-Feng Chang, Taichung, TW;
Chin-Huang Chang, Taichung Hsien, TW;
Siliconware Precision Industries Co., Ltd., Taichung, TW;
Abstract
A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficulty.