The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

May. 17, 2012
Applicants:

Hyeoung-won Seo, Gyeonggi-do, KR;

Yun-gi Kim, Gyeonggi-do, KR;

Young-woong Son, Gyeonggi-do, KR;

Bong-soo Kim, Gyeonggi-do, KR;

Inventors:

Hyeoung-Won Seo, Gyeonggi-do, KR;

Yun-Gi Kim, Gyeonggi-do, KR;

Young-Woong Son, Gyeonggi-do, KR;

Bong-Soo Kim, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/331 (2006.01); H01L 27/108 (2006.01); H01L 21/74 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10891 (2013.01); H01L 27/10894 (2013.01); H01L 27/10876 (2013.01); H01L 21/743 (2013.01); H01L 27/10823 (2013.01); H01L 27/10897 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.


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