The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Jun. 20, 2012
Applicants:

Ganming Qin, Chandler, AZ (US);

Edouard D. DE Frésart, Tempe, AZ (US);

Peilin Wang, Beijing, CN;

Pon S. Ku, Gilbert, AZ (US);

Inventors:

Ganming Qin, Chandler, AZ (US);

Edouard D. de Frésart, Tempe, AZ (US);

Peilin Wang, Beijing, CN;

Pon S. Ku, Gilbert, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/66734 (2013.01);
Abstract

A high voltage vertical field effect transistor device () is fabricated in a substrate () using angled implantations () into trench sidewalls formed above recessed gate poly layers () to form self-aligned N+ regions () adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer () formed over the recessed gate poly layers (), self-aligned P+ body contact regions () are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (-) and P+ body contact regions (-).


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