The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2014

Filed:

Dec. 01, 2011
Applicants:

Huajie Zhou, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Inventors:

Huajie Zhou, Beijing, CN;

Qiuxia Xu, Beijing, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); H01L 21/84 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/845 (2013.01); H01L 29/785 (2013.01); H01L 29/7851 (2013.01);
Abstract

The present application discloses a semiconductor Field-Effect Transistor (FET) structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising an SOI structure having a body-contact hole; forming a fin on the SOI structure of the semiconductor substrate; forming a gate stack structure on top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof becomes simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated; the present invention also is favorable for suppressing short channel effects desirably, and boosts MOSFETs to develop towards a trend of downscaling size.


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