The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Jun. 29, 2012
Applicants:

Chung Peng (Jackson) Kong, Tanjung Tokong, MY;

Chang-tsung Fu, Portland, OR (US);

Telesphor Kamgaing, Chandler, AZ (US);

Chan Kim Lee, Bayan Lepas, MY;

Ping Ping Ooi, Butterworth, MY;

Inventors:

Chung Peng (Jackson) Kong, Tanjung Tokong, MY;

Chang-Tsung Fu, Portland, OR (US);

Telesphor Kamgaing, Chandler, AZ (US);

Chan Kim Lee, Bayan Lepas, MY;

Ping Ping Ooi, Butterworth, MY;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

'Hybrid' transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels.


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