The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2014
Filed:
Oct. 24, 2011
Applicants:
Aritharan Thurairajaratnam, San Jose, CA (US);
David Senk, San Ramon, CA (US);
Inventors:
Aritharan Thurairajaratnam, San Jose, CA (US);
David Senk, San Ramon, CA (US);
Assignee:
Cisco Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 1/11 (2006.01); H05K 1/02 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 1/024 (2013.01); H05K 2201/09063 (2013.01); H05K 1/0251 (2013.01); H05K 1/116 (2013.01); H05K 3/429 (2013.01); H05K 2203/0242 (2013.01);
Abstract
A printed circuit board (PCB) stack-up has a signal via configured to transmit a signal through at least two different layers of the PCB stack-up, a reference structure that is at least a portion of a return path for the signal; and an unplated via disposed in an area surrounding the signal via. The unplated via is disposed in the area surrounding the signal via to improve the characteristic impedance of the signal via.