The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Mar. 12, 2013
Applicants:

Jong-min Baek, Suwon-si, KR;

In-sun Park, Seoul, KR;

Jong-myeong Lee, Seongnam-si, KR;

Jong-won Hong, Hwaseong-si, KR;

Hei-seung Kim, Suwon-si, KR;

Jung-soo Yoon, Hwaseong-si, KR;

Inventors:

Jong-Min Baek, Suwon-si, KR;

In-Sun Park, Seoul, KR;

Jong-Myeong Lee, Seongnam-si, KR;

Jong-Won Hong, Hwaseong-si, KR;

Hei-Seung Kim, Suwon-si, KR;

Jung-Soo Yoon, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76802 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming switching devices on a substrate. A lower structure is formed in the substrate having the switching devices. A lower conductive layer is formed on the lower structure. Sacrificial mask patterns are formed on the lower conductive layer. Lower conductive patterns are formed by etching the lower conductive layer using the sacrificial mask patterns as an etch mask. An interlayer insulating layer is formed on the substrate having the lower conductive patterns. Interlayer insulating patterns are formed by planarizing the interlayer insulating layer until the sacrificial mask patterns are exposed. Openings exposing the lower conductive patterns are formed by removing the exposed sacrificial mask patterns. Upper conductive patterns self-aligned with the lower conductive patterns are formed in the openings.


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