The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Jul. 09, 2010
Applicants:

Cryil Cabral, Jr., Mahopac, NY (US);

John M. Cotte, New Fairfield, CT (US);

Dinesh R. Koli, Tarrytown, NY (US);

Laura L. Kosbar, Mohegan Lake, NY (US);

Mahadevaiyer Krishnan, Hopewell Junction, NY (US);

Christian Lavoie, Pleasantville, NY (US);

Stephen M. Rossnagel, Pleasantville, NY (US);

Zhen Zhang, Ossining, NY (US);

Inventors:

Cryil Cabral, Jr., Mahopac, NY (US);

John M. Cotte, New Fairfield, CT (US);

Dinesh R. Koli, Tarrytown, NY (US);

Laura L. Kosbar, Mohegan Lake, NY (US);

Mahadevaiyer Krishnan, Hopewell Junction, NY (US);

Christian Lavoie, Pleasantville, NY (US);

Stephen M. Rossnagel, Pleasantville, NY (US);

Zhen Zhang, Ossining, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28512 (2013.01); H01L 21/28518 (2013.01); H01L 29/456 (2013.01);
Abstract

A method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.


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