The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Feb. 18, 2013
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Chih-Hung Hsueh, Tainan, TW;
Wei-Te Wang, Kaohsiung, TW;
Shao-Yu Chen, Tainan, TW;
Chun-Liang Fan, Tainan, TW;
Kuan-Chi Tsai, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to an integrated chip (IC) having an ultra-thick metal layer formed in a metal layer trench having a rounded shape that reduces stress between an inter-level dielectric (ILD) layer and an adjacent metal layer, and a related method of formation. In some embodiments, the IC has an inter-level dielectric layer disposed above a semiconductor substrate. The ILD layer has a cavity with a sidewall having a plurality of sections, wherein respective sections have different slopes that cause the cavity to have a rounded shape. A metal layer is disposed within the cavity. The rounded shape of the cavity reduces stress between the ILD layer and the metal layer to prevent cracks from forming along an interface between the ILD layer and the metal layer.