The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Aug. 30, 2012
Sung-soo Ahn, Gyeonggi-do, KR;
O Ik Kwon, Gyeonggi-do, KR;
Bum-soo Kim, Incheon, KR;
Hyun-sung Kim, Gyeonggi-do, KR;
Kyoung-sub Shin, Gyeonggi-do, KR;
Min-kyung Yun, Seoul, KR;
Seung-pil Chung, Seoul, KR;
Won-bong Jung, Gyeonggi-do, KR;
Sung-Soo Ahn, Gyeonggi-do, KR;
O Ik Kwon, Gyeonggi-do, KR;
Bum-Soo Kim, Incheon, KR;
Hyun-Sung Kim, Gyeonggi-do, KR;
Kyoung-Sub Shin, Gyeonggi-do, KR;
Min-Kyung Yun, Seoul, KR;
Seung-Pil Chung, Seoul, KR;
Won-Bong Jung, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.