The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Dec. 04, 2009
Applicants:

MI Sun Hwang, Gyunggi-do, KR;

Myung Sam Kang, Gyunggi-do, KR;

OK Tae Kim, Gyunggi-do, KR;

Seon Ha Kang, Gyunggi-do, KR;

Gil Yong Shin, Jeollabuk-do, KR;

Kil Yong Yun, Gyunggi-do, KR;

Min Jung Cho, Gyunggi-do, KR;

Inventors:

Mi Sun Hwang, Gyunggi-do, KR;

Myung Sam Kang, Gyunggi-do, KR;

Ok Tae Kim, Gyunggi-do, KR;

Seon Ha Kang, Gyunggi-do, KR;

Gil Yong Shin, Jeollabuk-do, KR;

Kil Yong Yun, Gyunggi-do, KR;

Min Jung Cho, Gyunggi-do, KR;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 3/36 (2006.01); H05K 3/10 (2006.01); H05K 3/20 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01);
U.S. Cl.
CPC ...
H05K 3/4685 (2013.01); H05K 3/421 (2013.01); H05K 3/205 (2013.01); H05K 2203/1536 (2013.01); H05K 3/0097 (2013.01); H05K 2201/0376 (2013.01); H05K 2203/0152 (2013.01);
Abstract

Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.


Find Patent Forward Citations

Loading…