The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Dec. 28, 2006
Applicants:

James Akiyama, Beaverton, OR (US);

William H. Clifford, Gig Harbor, WA (US);

Inventors:

James Akiyama, Beaverton, OR (US);

William H. Clifford, Gig Harbor, WA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01); G06F 13/16 (2006.01); G06F 12/06 (2006.01); G11C 11/408 (2006.01); G11C 8/12 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1684 (2013.01); G06F 12/0646 (2013.01); G11C 11/4082 (2013.01); G11C 8/12 (2013.01); G06F 12/0207 (2013.01); G09G 2360/122 (2013.01); G09G 2360/123 (2013.01);
Abstract

An embodiment of the present invention is a technique to control memory access. An address pre-swizzle circuit conditions address bits provided by a processor according to access control signals. A data steering circuit connects to N sub-channels of memory to dynamically steer data for a memory access type including tiled and untiled memory accesses according to the access control signals, the conditioned address bits, and sub-channel identifiers associated with the N sub-channels. The tiled memory access includes horizontally and vertically tiled memory accesses. An address post-swizzle circuit generates sub-channel address bits to the N sub-channels using the conditioned address bits and according to the access control signals and the sub-channel identifiers.


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