The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Dec. 13, 2013
Applicant:

Sandisk Technologies Inc., Plano, TX (US);

Inventors:

Mohan Dunga, Santa Clara, CA (US);

Sanghyun Lee, Davis, CA (US);

Masaaki Higashitani, Cupertino, CA (US);

Tuan Pham, San Jose, CA (US);

Assignee:

SanDisk Technologies Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); G11C 16/34 (2006.01); H01L 29/788 (2006.01); G11C 11/56 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); G11C 16/04 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); G11C 16/3418 (2013.01); H01L 29/7881 (2013.01); G11C 11/5642 (2013.01); H01L 27/11521 (2013.01); G11C 16/0408 (2013.01); H01L 27/11529 (2013.01); H01L 27/11524 (2013.01); H01L 21/28273 (2013.01);
Abstract

Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+.


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Dunga, Mohan. (2014). Method of forming pn floating gate non-volatile storage elements and transistor having n+ gate (U.S. Patent No. 8877627). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8877627

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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