The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2014
Filed:
Dec. 12, 2013
Stmicroelectronics (Crolles 2) Sas, Crolles, FR;
Stmicroelectronics S.a., Montrouge, FR;
Stmicroelectronics, Inc., Coppell, TX (US);
Commissariat À L'énergie Atomique ET Aux Énergies Alternatives, Paris, FR;
Claire Fenouillet-Beranger, Grenoble, FR;
Stephane Denorme, Crolles, FR;
Nicolas Loubet, Guilderland, NY (US);
Qing Liu, Guilderland, NY (US);
Emmanuel Richard, le Champ-Pres-Froges, FR;
Pierre Perreau, Varces, FR;
STMicroelectronics, Inc., Coppell, TX (US);
STMicroelectronics SA, Montrouge, FR;
STMicroelectronics (Crolles 2) SAS, Crolles, FR;
Commissariat à l'Énergie Atomique et aux Énergies Alternatives, Paris, FR;
Abstract
A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.