The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Dec. 17, 2012
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Yoo-Hyun Noh, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/792 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/792 (2013.01); H01L 27/11582 (2013.01); H01L 29/66833 (2013.01); H01L 29/66666 (2013.01); H01L 29/7926 (2013.01); H01L 27/11573 (2013.01);
Abstract

A method for fabricating a nonvolatile memory device includes forming a stacked structure over a substrate defining a cell area and a peripheral area and having a source region, the stacked structure including interlayer dielectric layers and sacrifice layers, forming channel layers connected to the substrate through the stacked structure of the cell area, forming a first slit in the stacked structure of the cell area, forming a second slit in the stacked structure, the second slit including a first portion and a second portion, removing the sacrifice layers exposed through the first and second slits, forming conductive layers to fill spaces from which the sacrifice layers are removed, forming an insulating layer in the second slit, and forming a source contact by burying a conductive material in the first portion of the second slit having the insulating layer formed therein.


Find Patent Forward Citations

Loading…